The present invention relates in general to memory devices, and, in particular, to an interleaved memory device readable in a synchronous mode for successive locations with a sequential or burst access mode.
Interleaved memory devices with a sequential (or burst) access mode comprises at least two banks of memory cells provided with their own address counter and independent decoding and sensing circuits. The array of memory cells may be subdivided in any number of blocks greater than two.
A typical simplified diagram of an interleaved memory device is depicted in FIG. 1. In a synchronous interleaved memory organized in two banks, the successive addresses of the respective banks at which the read operations must be alternately carried out are sequentially generated automatically by incrementing internal address counters in synchronization with an external clock. This is after a first random access to a certain location on one of the two banks based upon the acquisition of an externally commanded address (first asynchronous read cycle). The management of sequential read operations may be designed for any number of banks by reading the different banks according to a scheme while always incrementing the address of the previous location.
The fact that an interleaved memory is most commonly divided in two half-arrays or banks of cells allows for a new read cycle to be started on a bank while the read cycle on the other bank has not yet terminated, thus saving time. In order to do this it is essential that address operations to the two banks be independent from each other.
To maintain synchronization of the interleaved memory, increments for the address counter for the respective banks (EVEN/ODD) must be carried out according to whether the start address for a new sequential or burst access synchronous read phase pertains to the even or the odd bank. Also, it may pertain to a certain pre-established bank in case of a number of banks N greater than 2, according to the particular protocol used for managing the memory device. The start address is externally acquired and starts the first random access asynchronous read cycle.
In the most typical case of a two-bank interleaved memory, as may be observed in FIGS. 2 and 3, in a burst mode the read cycles successive to the first one are time interleaved between the banks ODD13 BANK and EVEN13 BANK. The increments of the address counters EVEN13 COUNTER and ODD13 COUNTER are controlled by two distinct incrementing clocks, labeled with INC13 EVEN and INC13 ODD in FIG. 4. This is produced by a control logic circuit that controls the timing of a synchronous read phase.
According to the known technique, each of the internal address counters of the respective half-arrays or banks is an N-th binary counter formed by N bistable stages, typically flip-flops, and N half-adder stages connected in cascade. Each half-adder stage has a carry bit input CARRY for the carry bit coming from the preceding stage and an address input coming from its associated flip-flop.
In such binary counters the propagation chain of the signal CARRY determines the maximum operating speed. In the propagation chain of the commonly used binary counters, carry bits are produced by ANDing the address bit and the carry bit coming from the previous stage. This imposes a wait for the propagation of signals throughout the Nxe2x88x921 stages in order to receive the information concerning the carry bit of the N-th stage. Such a propagation scheme implies wait times that often are not compatible with a high operating speed, especially in counters having a large number of stages.
In view of the foregoing background, it is an object of the present invention to provided an approach that addresses the slowness in generating addresses for the banks of an interleaved memory during a sequential access synchronous read phase.
This and other objects, advantages and features are provided by the fact that, differently from the common interleaved memory devices, only one internal address binary counter of one bank is used, while the function of an internal address counter of any other bank is performed by a common register in which it is copied the content (the internal address) of the binary counter of the first bank or of the content (the internal address) of the respective register of the bank that immediately precedes the considered bank according to the sequential read cycle scheme for all the memory banks, starting from the first one.
According to a preferred embodiment of the invention, each stage of the single internal address counter of one of the two banks is functionally coupled to a corresponding stage of the internal address register of the bank that follows it in the cycle succession of the sequential read of the data. The data is read from the different banks through a pass-gate that is switched to a conduction state by each increment pulse. Similarly, each stage (latch) of the register that follows the counter is coupled to the corresponding stage (latch) of the register that follows it in the succession through a pass-gate that is switched in a conduction state by each increment pulse.